Performance Analysis of Floating Point Multiplier Designs

Improved Floating-Point Matrix Multiplier

* This work is partially supported by NSC 99-2221-E-260-010-. † Correspondence to: D.-R. Duh; E-mail address: [email protected] Abstract – Floating-point matrix multiplier is widely used in scientific computations. A great deal of efforts has been made to achieve higher performance. The matrix multiplication consists of many multiplications and accumulations. Yang and Duh proposed a modular des...

NULL Convention Floating Point Multiplier

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The ...

Customising Floating-Point Designs

This paper describes a method for customising the representation of floating-point numbers that exploits the flexibility of reconfigurable hardware. The method determines the appropriate size of mantissa and exponent for each operation in a design, so that a cost function with a given error specification for the output relative to a reference representation can be satisfied. Currently our tool,...

On high-performance parallel decimal fixed-point multiplier designs

A Single Precision Asynchronous Floating Point Multiplier

This paper presents the delay of carry save based multiplier of 65nm technology using Field Programmable Gate Array is in enable mode. Here we present a design of floating point multiplication and that can utilize the decimal carry save addition is reduce path delay and dissipation power. The multiplier can stores a less number of multiplicand uses a decimal carry save addition in the portion o...